3. Documentation VC Compute Module Interface Board
Table of Contents
3.3 The CAM0 Socket
3.4 The CAM1 Socket
3.7 Real Time Clock
3.8 JTAG Connector
4. FPGA Setup
5.1 Preparation
6. Accessories
1 General Information
The VC Compute Module Interface Board (CMI) is designed for a RaspberryPi CM3 Compute Module and CM3+. It has two MIPI connectors for connecting camera sensors. There are pins for triggering the image sensors and flash output pins with configurable current where several Power LEDs may be driven directly. The board features mounting options for our LED flash rings and camera sensors. Moreover it features an ethernet socket and an USB port as well as four PLC input and output lanes. There is also an Micro-SD card slot and a real time clock (RTC). A FPGA for managing triggering/flashing and input/output mappings is pre-programmed, but can also be reprogrammed directly by the customer.
2 Technical Specifications
Technical Data
Component / Feature | Specification |
|---|---|
Dimensions | 125 x 57 x 30 mm (without mounting LED ring) |
Trigger input | Opto-isolated, 8 mA @ 5 V |
Process interface | PLC: 4 inputs / 4 outputs, outputs 4×200 mA, FPGA IO: 4 Digital LVCMOS (3.3 V) GPIOs |
Trigger | 1 flash trigger output at 24 V, 1 trigger input |
LED driver | 2 LED driver outputs (1 shared with flash trigger output) |
Ethernet interface | 1000 Mbit/s |
Serial interface | Available as RS-232 interface |
Storage Conditions | Temperature: -20 to +60 °C, Max. humidity: 90%, non condensing. |
Operating Conditions | Temperature: 0 to +50 °C, Max. humidity: 80%, non condensing. |
Nominal voltage Vdd for power supply | 12–24 V DC |
Nominal Power consumption | 12 W (max, dependent on many things like hardware connected over USB, Flash LEDs, etc.) not including PLC outputs |
3 Hardware Interfaces
VC CMI socket overview
(Top view)
VC CMI block diagram
VC CMI default FPGA block diagram
3.1 Power, Trigger and PLC Connector POWIO
Pin Assignment of POWIO Connector (DSUB - male)
CMI Socket Frontal View | Pin | Signal | Level |
|---|---|---|---|
| 1 | Main Power Supply | Vdd |
2 | Common Ground | GND | |
3 | PLC In0 | +5–24 V | |
4 | PLC Out0 | Vdd | |
5 | PLC In1 | +5–24 V | |
6 | PLC Out1 | Vdd | |
7 | PLC Out2 | Vdd | |
8 | PLC In2 | +5–24 V | |
9 | PLC Out3 | Vdd | |
10 | PLC In3 | +5–24 V | |
11 | FLASH0 | Vdd 0–1.5 A | |
12 | FLASH1 | Vdd 0–1.5 A | |
13 | N/C | — | |
14 | TrigIn_P | +5 V | |
15 | TrigIn_M | GND |
All inputs are 5–24 V, 2.4 mA @ 5 V and 5 mA @ 24 V, 200 kHz max., threshold: positive +1.3 mA typ., negative 0.7 mA typ.
3.1.1 POWIO PLC IOs
Electrical Specifications of digital PLC IOs
Separation of PLC/trigger output voltage | PLC outputs supply not separated from power supply |
PLC Input Voltage | Identical with power supply voltage |
PLC Input Current (max) | 2.4 mA @ 5 V and 5 mA @ 24 V, 200 kHz max., threshold: positive +1.3 mA typ., negative 0.7 mA typ. |
PLC Output Voltage | Identical with power supply Voltage — internally connected |
PLC Output Current (max) | 4 × 200 mA Max total of all outputs: 0.8 A |
Max Current for 1 Power / PLC connector pin | 200 mA |
Power failure detection | Poly Fuse |
The maximum combined current of all outputs should not exceed 1 A.
3.1.2 POWIO Trigger Input
Electrical Specifications of the trigger Input
Separation of trigger input | Yes, optically isolated, 8 mA @ 5 V |
3.1.3 POWIO/LED A Flash Output
The Hardware features two independently adjustable current sources for the connection of two LED light sources. They are designed for controlling the ring illuminators around the lens, connected to LED A. They are also accessible over the connector POWIO.
The controller covers a current range from 150 to 1500 mA.
The duty cycle is limited to 1:8, i.e. the off-state is eight times longer than the on-state for the output. Example: 1 ms flash duration, 8 ms cool down duration.
The default FPGA has a protection which limits the maximum flash duration to 2 ms. This is to protect LEDs which cannot support 1.5 A over a longer time period. For developping own LED rings, there is also an analogue protection at FLASH1 while the FLASH0 can theoretically support 1.5 A steady (please note, that this current is not calculated to the nominal power consumption).
Technical Data for each LED Controller
Iout | 150–1500 mA, programmable |
Uout | 4–16 V (1–4 LEDs in series depending on the Vf) |
Do not connect inductive loads to FLASH0 or FLASH1 outputs!
The default FPGA limits the maximum flash duration to 2 ms of both flash outputs for LED protection, while FLASH1 is additionally limited by a slower analogue protection circuit.
FLASH0 and FLASH1 behave different: While the FLASH0 output can be used for triggering, the FLASH1 output is not intended for triggering external flash!
FLASH1 has a small steady current flow for providing an instant power supply. This may lead to dark glimming LEDs connected to the FLASH1 output while LEDs connected to the FLASH0 output won't emit light (i.e. one half of a VC LED ring would glow).
3.1.3.1 Connection of Flash Outputs: External Flash
The figure shows how to connect an external flash illumination to FLASH0/TrigOut signal by using an opto isolation. R limit should be chosen to protect the opto isolator, e.g. 2K2/250 mW for a current of 10 mA. Remark: R limit is not necessary for Vision Components' High Power IR Illumination (VK002180). The current source should be set to 500 mA.
FLASH1 output is not intended for triggering an external flash!
3.1.3.2 Connection of Flash Outputs: Direct High-Power-LEDs
The figure shows how to connect an external flash illumination. The current source should be set to the required current setting between 200 and 1500 mA. The time limit must be set to an appropriate value for the protection of the LEDs according to the data sheet of the manufacturer. Connectable are 1 to 6 High Power LEDs.
3.1.3.3 Connection of Flash Outputs: PLC
The figure shows how to connect a PLC to the FLASH0/TrigOut or FLASH1 signal. The current source should be set to 500 mA.
FLASH1 output is not intended for triggering an external flash!
3.1.3.4 Connection of LED Rings over LED A: Internal Flash
Pin Assignment of LED A and LED B Connector
Camera Socket Top View | Pin | LED A Signal | LED B Signal |
|---|---|---|---|
1 | GND | GND | |
2 | N/C | N/C | |
3 | FLASH0 | N/C | |
4 | FLASH1 | N/C |
The current source should be set to the required current setting between 200 and 1500 mA. The time limit must be set to an appropriate value for the protection of the LEDs according to the data sheet of the manufacturer.
Be careful not to produce a short circuit between the VC MIPI sensor (which has a grounded surface) and the LED ring!
3.2 RS-232 and FPGAIO Connector RSIO
A FPGA IO connects to the onboard FPGA which itself may also be programmed to have connections to some RaspberryPi GPIOs.
Pin Assignment of RSIO Connector
Camera Socket Top View | Pin | Signal | Additional Information |
|---|---|---|---|
1 | V24_TxD | Native RS-232 interface | |
2 | +3.3 V | — | |
3 | V24_RxD | Native RS-232 interface | |
4 | FPGA IO 1 | Digital LVCMOS (3.3 V) | |
5 | GND | — | |
6 | FPGA IO 2 | Digital LVCMOS (3.3 V) | |
7 | FPGA IO 0 | Digital LVCMOS (3.3 V) | |
8 | FPGA IO 3 | Digital LVCMOS (3.3 V) |
FPGA IO signals are LVCMOS 3.3 V.
The FPGA IO I/Os are very sensitive (also to ESD) and not galvanically separated. Opto-isolation of the driving circuit is therefore strongly recommended. It is also recommended to keep the cable as short as possible!
The I/Os are not protected against over current. The I/Os are neither protected against short circuit nor reverse voltage spikes from inductive loads.
Be careful: Reversing the connector is not allowed and may damage the board!
3.3 The CAM0 Socket
The RaspberryPi Naming for the camera interfaces CAM?_… are represented at this document by the more generic ones CSI?_… (camera serial interface).
The CAM0 Socket connects to CSI0 but to I2C1 for compatibility. The CAM0 Socket only supports 2 MIPI data lanes in contrast to the CAM1 socket with 4 lanes.
Beneath the CAM0 socket is a LED which emits green light if the CAM0 socket is powered.
Pin connections of the CAM0 Socket
Camera Socket | Pin | Signal |
|---|---|---|
| 1 | +3.3 V |
2 | I2C1 SDA | |
3 | I2C1 SCL | |
4 | GND | |
5 | FPGA CAM0 FLASH | |
6 | FPGA CAM0 TRIG | |
7 | GND | |
8 | N/C | |
9 | N/C | |
10 | GND | |
11 | N/C | |
12 | N/C | |
13 | GND | |
14 | CSI0 CP | |
15 | CSI0 CN | |
16 | GND | |
17 | CSI0 DP1 | |
18 | CSI0 DN1 | |
19 | GND | |
20 | CSI0 DP0 | |
21 | CSI0 DN0 | |
22 | GND |
3.4 The CAM1 Socket
The CAM1 socket connects to CSI1 but to I2C0 for compatibility. Only this Socket supports 4 MIPI data lanes.
Beneath the CAM1 socket is a LED which emits green light if the CAM1 socket is powered.
Pin connections of the CAM1 Socket
Camera Socket | Pin | Signal |
|---|---|---|
| 1 | +3.3 V |
2 | I2C0 SDA | |
3 | I2C0 SCL | |
4 | GND | |
5 |