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3. Documentation VC Compute Module Interface Board

3. Documentation VC Compute Module Interface Board

Owned by Wilhelm Scheermann
Last updated: Aug 21, 2024 by Charlotte Quirmbach (Unlicensed)
16 min read

 

 

Table of Contents

  1. General Information

  2. Technical Specifications

  3. Hardware Interfaces

3.1 Power, Trigger and PLC Connector POWIO

3.2 RS-232 and FPGA IO Connector RSIO

3.3 The CAM0 Socket

3.4 The CAM1 Socket

3.5 Display Interface Connector DISP1

3.6 RaspberryPi Compute Module Connector

3.7 Real Time Clock

3.8 JTAG Connector

4. FPGA Setup

5. Software Setup

5.1 Preparation

5.2 Driver Installation

5.3 GPIO Software Setup

5.4 Setting Flash Currents

5.5 Activating Flash output

6. Accessories

6.1 Order numbers of all available Accessories

 

1   General Information

The VC Compute Module Interface Board (CMI) is designed for a RaspberryPi CM3 Compute Module and CM3+. It has two MIPI connectors for connecting camera sensors. There are pins for triggering the image sensors and flash output pins with configurable current where several Power LEDs may be driven directly. The board features mounting options for our LED flash rings and camera sensors. Moreover it features an ethernet socket and an USB port as well as four PLC input and output lanes. There is also an Micro-SD card slot and a real time clock (RTC). A FPGA for managing triggering/flashing and input/output mappings is pre-programmed, but can also be reprogrammed directly by the customer.

 

2   Technical Specifications

Technical Data

Component / Feature

Specification

Component / Feature

Specification

Dimensions

125 x 57 x 30 mm (without mounting LED ring)

Trigger input

Opto-isolated, 8 mA @ 5 V

Process interface

PLC: 4 inputs / 4 outputs, outputs 4×200 mA, FPGA IO: 4 Digital LVCMOS (3.3 V) GPIOs

Trigger

1 flash trigger output at 24 V, 1 trigger input

LED driver

2 LED driver outputs (1 shared with flash trigger output)

Ethernet interface

1000 Mbit/s

Serial interface

Available as RS-232 interface

Storage Conditions

Temperature: -20 to +60 °C, Max. humidity: 90%, non condensing.

Operating Conditions

Temperature: 0 to +50 °C, Max. humidity: 80%, non condensing.

Nominal voltage Vdd for power supply

12–24 V DC

Nominal Power consumption

12 W (max, dependent on many things like hardware connected over USB, Flash LEDs, etc.) not including PLC outputs

 

3   Hardware Interfaces

VC CMI socket overview

(Top view)

VC CMI block diagram

VC CMI default FPGA block diagram

3.1 Power, Trigger and PLC Connector POWIO

Pin Assignment of POWIO Connector (DSUB - male)

CMI Socket Frontal View

Pin

Signal

Level

CMI Socket Frontal View

Pin

Signal

Level

 

1

Main Power Supply

Vdd

2

Common Ground

GND

3

PLC In0

+5–24 V

4

PLC Out0

Vdd

5

PLC In1

+5–24 V

6

PLC Out1

Vdd

7

PLC Out2

Vdd

8

PLC In2

+5–24 V

9

PLC Out3

Vdd

10

PLC In3

+5–24 V

11

FLASH0

Vdd 0–1.5 A

12

FLASH1

Vdd 0–1.5 A

13

N/C

—

14

TrigIn_P

+5 V

15

TrigIn_M

GND

All inputs are 5–24 V, 2.4 mA @ 5 V and 5 mA @ 24 V, 200 kHz max., threshold: positive +1.3 mA typ., negative 0.7 mA typ.

 

3.1.1 POWIO PLC IOs

Electrical Specifications of digital PLC IOs

Separation of PLC/trigger output voltage

PLC outputs supply not separated from power supply

PLC Input Voltage

Identical with power supply voltage

PLC Input Current (max)

2.4 mA @ 5 V and 5 mA @ 24 V, 200 kHz max., threshold: positive +1.3 mA typ., negative 0.7 mA typ.

PLC Output Voltage

Identical with power supply Voltage — internally connected

PLC Output Current (max)

4 × 200 mA Max total of all outputs: 0.8 A

Max Current for 1 Power / PLC connector pin

200 mA

Power failure detection

Poly Fuse

The maximum combined current of all outputs should not exceed 1 A.

 

3.1.2   POWIO Trigger Input

Electrical Specifications of the trigger Input

Separation of trigger input

Yes, optically isolated, 8 mA @ 5 V

 

3.1.3   POWIO/LED A Flash Output

The Hardware features two independently adjustable current sources for the connection of two LED light sources. They are designed for controlling the ring illuminators around the lens, connected to LED A. They are also accessible over the connector POWIO.

The controller covers a current range from 150 to 1500 mA.

The duty cycle is limited to 1:8, i.e. the off-state is eight times longer than the on-state for the output. Example: 1 ms flash duration, 8 ms cool down duration.

The default FPGA has a protection which limits the maximum flash duration to 2 ms. This is to protect LEDs which cannot support 1.5 A over a longer time period. For developping own LED rings, there is also an analogue protection at FLASH1 while the FLASH0 can theoretically support 1.5 A steady (please note, that this current is not calculated to the nominal power consumption).

Technical Data for each LED Controller

Iout

150–1500 mA, programmable

Uout

4–16 V (1–4 LEDs in series depending on the Vf)

Do not connect inductive loads to FLASH0 or FLASH1 outputs!

The default FPGA limits the maximum flash duration to 2 ms of both flash outputs for LED protection, while FLASH1 is additionally limited by a slower analogue protection circuit.

FLASH0 and FLASH1 behave different: While the FLASH0 output can be used for triggering, the FLASH1 output is not intended for triggering external flash!

FLASH1 has a small steady current flow for providing an instant power supply. This may lead to dark glimming LEDs connected to the FLASH1 output while LEDs connected to the FLASH0 output won't emit light (i.e. one half of a VC LED ring would glow).

3.1.3.1   Connection of Flash Outputs: External Flash

The figure shows how to connect an external flash illumination to FLASH0/TrigOut signal by using an opto isolation. R limit should be chosen to protect the opto isolator, e.g. 2K2/250 mW for a current of 10 mA. Remark: R limit is not necessary for Vision Components' High Power IR Illumination (VK002180). The current source should be set to 500 mA.

FLASH1 output is not intended for triggering an external flash!

 

3.1.3.2   Connection of Flash Outputs: Direct High-Power-LEDs

The figure shows how to connect an external flash illumination. The current source should be set to the required current setting between 200 and 1500 mA. The time limit must be set to an appropriate value for the protection of the LEDs according to the data sheet of the manufacturer. Connectable are 1 to 6 High Power LEDs.

3.1.3.3   Connection of Flash Outputs: PLC

The figure shows how to connect a PLC to the FLASH0/TrigOut or FLASH1 signal. The current source should be set to 500 mA.

FLASH1 output is not intended for triggering an external flash!

3.1.3.4   Connection of LED Rings over LED A: Internal Flash
Pin Assignment of LED A and LED B Connector

Camera Socket Top View

Pin

LED A Signal

LED B Signal

Camera Socket Top View

Pin

LED A Signal

LED B Signal

1

GND

GND

2

N/C

N/C

3

FLASH0

N/C

4

FLASH1

N/C

The current source should be set to the required current setting between 200 and 1500 mA. The time limit must be set to an appropriate value for the protection of the LEDs according to the data sheet of the manufacturer.

Be careful not to produce a short circuit between the VC MIPI sensor (which has a grounded surface) and the LED ring!

 

3.2 RS-232 and FPGAIO Connector RSIO

A FPGA IO connects to the onboard FPGA which itself may also be programmed to have connections to some RaspberryPi GPIOs.

Pin Assignment of RSIO Connector

Camera Socket Top View

Pin

Signal

Additional Information

Camera Socket Top View

Pin

Signal

Additional Information

1

V24_TxD

Native RS-232 interface

2

+3.3 V

—

3

V24_RxD

Native RS-232 interface

4

FPGA IO 1

Digital LVCMOS (3.3 V)

5

GND

—

6

FPGA IO 2

Digital LVCMOS (3.3 V)

7

FPGA IO 0

Digital LVCMOS (3.3 V)

8

FPGA IO 3

Digital LVCMOS (3.3 V)

 

3.3 The CAM0 Socket

The CAM0 Socket connects to CSI0 but to I2C1 for compatibility. The CAM0 Socket only supports 2 MIPI data lanes in contrast to the CAM1 socket with 4 lanes.

Beneath the CAM0 socket is a LED which emits green light if the CAM0 socket is powered.

Pin connections of the CAM0 Socket

Camera Socket

Pin

Signal

Camera Socket

Pin

Signal

 

1

+3.3 V

2

I2C1 SDA

3

I2C1 SCL

4

GND

5

FPGA CAM0 FLASH

6

FPGA CAM0 TRIG

7

GND

8

N/C

9

N/C

10

GND

11

N/C

12

N/C

13

GND

14

CSI0 CP

15

CSI0 CN

16

GND

17

CSI0 DP1

18

CSI0 DN1

19

GND

20

CSI0 DP0

21

CSI0 DN0

22

GND

3.4 The CAM1 Socket

The CAM1 socket connects to CSI1 but to I2C0 for compatibility. Only this Socket supports 4 MIPI data lanes.

Beneath the CAM1 socket is a LED which emits green light if the CAM1 socket is powered.

Pin connections of the CAM1 Socket

Camera Socket

Pin

Signal

Camera Socket

Pin

Signal

 

1

+3.3 V

2

I2C0 SDA

3

I2C0 SCL

4

GND

5

FPGA CAM1 FLASH

6

FPGA CAM1 TRIG

7

GND

8

CSI1 DP3

9

CSI1 DN3

10

GND

11

CSI1 DP2

12

CSI1 DN2

13

GND

14

CSI1 CP

15

CSI1 CN

16

GND

17

CSI1 DP1

18

CSI1 DN1

19

GND

20

CSI1 DP0

21

CSI1 DN0

22

GND

3.5 Display Interface Connector DISP1

The DISP1 Socket connects to DSI1 but to I2C0 for compatibility.

Pin Assignment of DISP1 Connector

Display Socket Top View

Pin

Signal

Display Socket Top View

Pin

Signal

 

1

GND

2

DSI1 DN1

3

DSI1 DP1

4

GND

5

DSI1 CN

6

DSI1 CP

7

GND

8

DSI1 DN0

9

DSI1 DP0

10

GND

11

I2C0 SCL

12

I2C0 SDA

13

GND

14

+3.3 V

15

+3.3 V

16–30

N/C

The display itself needs the dt-blob.bin generated from the dt-blob.dts and copied into the /boot (not /boot/overlays) directory.

3.6 RaspberryPi Compute Module Connector

3.6.1 RaspberryPi GPIO Connections

GPIO Connections at RaspberryPi

GPIO-Nr.

Direction

Connects to

GPIO-Nr.

Direction

Connects to

GPIO 0

I/O

I2C0 SDA

GPIO 1

I/O

I2C0 SCL

GPIO 2

I/O

I2C1 SDA

GPIO 3

I/O

I2C1 SCL

GPIO 4

I/O

FPGA RPI GPIO A

GPIO 5

I/O

FPGA RPI GPIO B

GPIO 6

I/O

FPGA RPI GPIO C

GPIO 7

I/O

FPGA RPI GPIO D

GPIO 8

I/O

FPGA SPI0 CE0 N

GPIO 9

I/O

FPGA SPI0 MISO

GPIO 10

I/O

FPGA SPI0 MOSI

GPIO 11

I/O

FPGA SPI0 SCLK

GPIO 12

I/O

FPGA RPI GPIO E

GPIO 13

I/O

FPGA RPI GPIO F

GPIO 14

I/O

RSIO V24_TxD

GPIO 15

I/O

RSIO V24_RxD

GPIO 16

I/O

FPGA RPI GPIO G

GPIO 17

I/O

FPGA RPI GPIO H

GPIO 18

I/O

FPGA RPI GPIO I

GPIO 19

I/O

FPGA RPI GPIO J

GPIO 20

I/O

FPGA RPI GPIO K

GPIO 21

I/O

FPGA RPI GPIO L

GPIO 22

N/C

—

GPIO 23

I/O

FPGA I2C SDA

GPIO 24

I/O

FPGA I2C SCL

GPIO 25

N/C

—

GPIO 26

N/C

—

GPIO 27

N/C

—

GPIO 28

INPUT

PULLDOWN

GPIO 29

INPUT

PULLDOWN

GPIO 30

N/C

—

GPIO 31

N/C

—

GPIO 32

N/C

—

GPIO 33

N/C

—

GPIO 34

I/O

SD1 CLK

GPIO 35

I/O

SD1 CMD

GPIO 36

I/O

SD1 DAT0

GPIO 37

I/O

SD1 DAT1

GPIO 38

I/O

SD1 DAT2

GPIO 39

I/O

SD1 DAT3

GPIO 40

I/O

SD1 DAT4

GPIO 41

I/O

SD1 DAT5

GPIO 42

I/O

SD1 DAT6

GPIO 43

I/O

SD1 DAT7

GPIO 44

INPUT

PULLDOWN

GPIO 45

INPUT

PULLDOWN

3.6.1 RaspberryPi USB Connections

The Pins USB DP and USB DM connect to an USB hub with two devices attached:

  • Gigabit Ethernet, and

  • the USB socket.

The hub is driven by a 24 MHz clock by the default FPGA.

 

3.7 Real Time Clock

The Maxim DS1374 RTC is connected to the FPGA I2C bus. It is accessible over address 0x68. An accumulator which buffers the RTC must be activated to be charged: The only allowed values for register 0x09 to be written are 0xaa for charging, and 0x00.

Example

This is a low-level approach as root. We assume the RTC is already detected as 0x68 at I2C bus 3, check with:

i2detect 3

beforehand. This sequence should activate charging:

modprobe -r rtc_ds1374

i2ctransfer -y 3 w2@0x68 0x09 0xaa

i2ctransfer -y 3 w1@0x68 0x09 r1@0x68

modprobe rtc-ds1374

hwclock --systohc

hwclock -r

 

3.8 JTAG Connector

The JTAG connector is the JTAG interface for programming the onboard FPGA.

Pin Assignment of the JTAG Connector

Camera Socket Top View

Pin